MA2-P1: VLSI System-on-Chip Integrated Multimedia Systems |
| Session Type: Poster |
| Time: Monday, July 10, 10:50 - 11:50 |
| Location: Toronto III |
| Chair: Liang-Gee Chen, National Taiwan University |
| MA2-P1.1: A HIGH THROUGHPUT VLSI ARCHITECTURE DESIGN FOR H.264 CONTEXT-BASED ADAPTIVE BINARY ARITHMETIC DECODING WITH LOOK AHEAD PARSING |
| Yao-Chang Yang; National Chung Cheng University |
| Chien-Chang Lin; National Chung Cheng University |
| Hsui-Cheng Chang; National Chung Cheng University |
| Ching-Lung Su; National Yunlin University of Science and Technology |
| Jiun-In Guo; National Chung Cheng University |
| MA2-P1.2: AN EFFICIENT REFERENCE FRAME STORAGE SCHEME FOR H.264 HDTV DECODER |
| Peng Zhang; Chinese Academy of Sciences |
| Wen Gao; Chinese Academy of Sciences |
| Di Wu; Chinese Academy of Sciences |
| Don Xie; Grandview Semiconductor |
| MA2-P1.3: SCALABLE RATE-DISTORTION-COMPUTATION HARDWARE ACCELERATOR FOR MCTF AND ME |
| Yi-Hau Chen; National Taiwan University |
| Ching-Yeh Chen; National Taiwan University |
| Chih-Chi Cheng; National Taiwan University |
| Liang-Gee Chen; National Taiwan University |
| MA2-P1.4: A NOVEL DATA-PARALLEL COPROCESSOR FOR MULTIMEDIA SIGNAL PROCESSING |
| Lai Mingche; National University of Defense Technology |
| Dai Kui; National University of Defense Technology |
| Lu Hongyi; National University of Defense Technology |
| Wang Zhiying; National University of Defense Technology |